The present invention relates generally to data transmission systems, and more particularly to serial data transmission systems for transmitting data words in a sequence of data bits.
Data transmission systems require a clock to coordinate transmission of data.
Traditional serial transmission systems require a data line and three clocks—a word clock, a high frequency bit clock, and a high frequency system clock. Example values for these lines are as follows: word clock at 48 Khz, bit clock at 3.072 MHz, a system clock at 12.288 MHz and a data line that sends data at the 3.072 MHz rate. An example system that uses multiple clock signals is the system described in U.S. Pat. No. 4,755,817 to Vandenbulke et al. that uses two high-frequency clock signals to transmit data words.
The use of a plurality of clocks increases the size of an interface between a transmitter and receiver. The use of high frequency clocks in an interface generates undesirable radio frequency (RF) emissions. Circuit designers have created expensive system serial transmission systems in order to attempt to compensate for the large interface requirements and to comply with emission standards.
Conventional systems typically output a word during a signal high time and another word during a signal low time. Therefore, these systems require a word clock with a specified duty cycle to ensure time on each level for the output of a word. The typical duty cycle is fifty percent. A duty cycle is the ratio of signal high time to signal low time. If such a clock is not readily available to the designer, the system may require additional circuitry.
Conventional transmitters and receivers are not integrated onto a single chip due to the size of the phase locked loop (PLL) typically included in the devices. A loop filter in the conventional PLL is composed of a resistor and capacitor where the size of the combination of these elements is too large for a single chip. Using more than one chip for the transmitter or receiver increases the cost and size of the system. Therefore, it is desirable to have a receiver and transmitter that are each integrated onto a single chip.